With the increasingly high display resolution, traditional interfaces such as VGA, DVI and the like could not meet the visual demands of people. Novel digital interfaces represented by HDMI and Displayport are accordingly available.
In terms of an internal interface, an internal interface eDP (Embedded Displayport) of Displayport is produced to gradually replace the traditional LVDS.
Taking a condition in which full high definition (FHD) resolution (1920*1080) is achieved as an example, if an existing mobile industry processor interface (MIPI) is used as the internal interface of a device, at least four lanes are needed to transmit data, whereas if the eDP interface is used as the internal interface of the device, only two lanes are needed, thus compared with the MIPI interface, by adopting the eDP interface, the number of control lines may be decreased.
Meanwhile, since eDP interface protocol adopts an embedded clock signal, and MIPI protocol adopts a pair of clock signals which are separated provided, an eDP interface module has significant anti-electromagnetic interference capability, and the eDP interface may further reduce power consumption by automatically refreshing, reducing amplitude of fluctuation in power consumption, additionally providing connection options, compressing transmission data, controlling regional backlight, etc., so as to prolong the service life of a battery.
FIG. 1 is a schematic diagram of a structure of an eDP interface in the prior art. As shown in FIG. 1, the traditional eDP interface includes a clock signal generating module and an eDP data processing chip. The eDP data processing chip processes data according to a clock signal generated by the clock signal generating module and sends the processed data to a lane for transmission.
The transmission rate in a traditional eDP protocol is fixed, namely, the eDP interface includes four lanes, in each of which the transmission rate may only be one of 1.62 Gbps, 2.7 Gbps and 5.4 Gbps. The transmission rate of a lane is controlled by a clock signal, for example, if the frequency of the clock signal is a first frequency, the processing speed of the eDP data processing chip is 1.62 Gbps, and the transmission rate of the corresponding lane is 1.62 Gbps; if the frequency of the clock signal is a second frequency, the processing speed of the eDP data processing chip is 2.7 Gbps, and the transmission rate of the corresponding lane is 2.7 Gbps; if the frequency of the clock signal is a third frequency, the processing speed of the eDP data processing chip is 5.4 Gbps, and the transmission rate of the corresponding lane is 5.4 Gbps. In a transmission process, one, two or four lane(s) may be selected to transmit data according to actual demand so as to support corresponding resolution. When multiple lanes are used for transmission, the transmission rate of each lane is the same.
Since the transmission rate of the lane is defined in the traditional eDP protocol, the existing eDP interface can only support limited types of transmission rates (each lane has three transmission rates, and the selection of lane number has three options, thus nine transmission rates are supported in total), and the applicable resolution types are very limited, thereby limiting the use of the eDP interface.